The present invention relates to a semiconductor integrated circuit equipped with a regulator circuit, and particularly to a regulator circuit which controls an output voltage according to an increase or decrease in load current consumed by a load circuit coupled to an output terminal.
In products each of which utilizes a semiconductor process subsequent to 28 nm-generation, the operation of a semiconductor device has been expected to become faster. A problem, however, arises in that since current density in a chip becomes high as the generation of a semiconductor process proceeds, the voltage to be applied to a transistor is greatly reduced at a high load/high-speed operation as compared with at a low load/low-speed operation, thus resulting in a difficulty of a high-speed operation. Under such a circumstance, there has generally been adopted a method for mounting a regulator circuit over a semiconductor chip and suppressing a fluctuation in the voltage applied to a transistor. In general, analog parts such as a resistor, a capacitor, an inductor, etc. are used in a regulator circuit, and a control algorithm for controlling the voltage by the combination of parameter values for these elements has been implemented. The type of such a regulator circuit is called an analog control type regulator. It is difficult for the analog control type regulator to change the loop characteristics of control according to a target to be controlled, at debug after the manufacture of the chip. This is because it is difficult to greatly change the parameter values for the analog parts for determining the loop characteristics. On the other hand, there has been proposed a digital control type regulator capable of easily changing loop characteristics even after chip design.
An example of a regulator circuit operated by such digital control has been disclosed in each of Non-Patent Documents 1 through 3, for example. There has been disclosed in the Non-Patent Document 1, an example in which a voltage value obtained by monitoring an output voltage is converted to a digital value, and a power MOS transistor is controlled by PID control. There has been disclosed in the Non-Patent Document 2, an example in which the number of power MOS transistors each brought to a conducting state is sequentially increased using shift registers. There has been disclosed in the Non-Patent Document 3, an example in which the gate length of a power MOS transistor is increased along a linear function.